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ICPL2631
Dual High CMR, High Speed Optoisolator

Circuit and Package
Features
Description
Absolute Maximum Ratings
Recommended Operating Conditions
Electrical Characteristics
Switching Characteristics

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Circuit and Package

Units: mm DIL
a 0-13 degrees
b 6.10-6.60
d 2.54 Typ
f 3.29 Min
h 3.25-3.75
k 0.48-0.56 tip,1.1-1.4 shoulder
l 9.40-9.90
s 7.62 Typ
x 0.20-0.30

Features

LSTTL/TTL Compatible
High Speed
High Density Packaging
Guaranteed Performance Over Temperature
Internal Shield for High Common Mode Rejection

Description

The ICPL2631 consists of a pair of GaAsP emitting diodes and integrated high gain photodetectors. Internal shields provide a guaranteed common mode transient immunity of 1000V/µs. LSTTL and TTL logic compatibility is achieved with a typical propagation delay of 45 ns. Surface Mount Option Available.
All electrical parameters are 100% tested. Specifications are guaranteed to a cumulative 0.65% AQL.

Absolute Maximum Ratings (25°C)

Storage Temperature:
Operating Temperature:
Lead Soldering:		 -55°C to +125°C
0°C to +70°C
260°C for 10s, 1.6mm below seating plane

Input Diode (each channel)

Average Forward Current IF:
Reverse Voltage VR:		 15mA (note 2)
5V

Output Transistor (each channel)

Supply Voltage VCC:
Current IO:
Voltage VO:
Collector Power Dissipation:		 7V (1 minute max)
16mA
7V
40mW

Recommended Operating Conditions

PARAMETER SYMBOL MIN MAX UNIT
Input Current, Low Level (each channel) IFL
250 µA
Input Current, High Level (each channel) IFH 6.3 (*) 15 mA
Supply Voltage, Output VCC 4.5 5.5 V
Fan Out (TTL Load) (each channel) N
8
Operating Temperature TA 0 70 °C

* 6.3mA condition permits at least 20% CTR degradation guardband. Initial switching threshold is 5mA or less.

Electrical Characteristics

(Over recommended temperature Ta= 0°C to 70°C u.o.s.; all typical values at Vcc=5V, Ta=25°C u.o.s.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT NOTES
IOH High Level Output Current VCC=VO=5.5V, IF=250µA
30 250 µA 3
VOL Low Level Output Voltage VCC=5.5V, IF=5mA, IOL(sinking)=13mA
0.5 0.6 V 3
ICCH High Level Supply Current VCC=5.5V, IF=0, (both channels)
15 30 mA
ICCL Low Level Supply Current VCC=5.5V, IF=10mA, (both channels)
32 38 mA
IIO Input-Output Leakage Current RH=45%, TA=25°C, t=5s, VIO=3000Vdc

1.0 µA 4,5
RIO Resistance VIO=500V
1000
Gohm 4
CIO Capacitance f=1MHz
0.6
pF 4
VF Input Forward Voltage IF=10mA, TA=25°C
1.5 1.75 V 3
BVR Input Reverse Breakdown Voltage IR=10µA, TA=25°C 5

V 3
CIN Input Capacitance VF=0, f=1MHz
60
pF 3
dVF/dTA Input Diode Temperature Coefficient IF=10mA -1.8 mV/°C
III Input-Input Leakage Current RH=45%, VII=500V, t=5s 0.01 µA 6
RII Resistance Input - Input VII=500V 100 Gohm 6
CII Capacitance Input - Input f=1MHz 0.27 pF 6

Switching Characteristics (Ta=25°C, Vcc=5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT NOTES
tPLH Propagation Delay Time to High Output Level RL=350ohm, CL=15pF, IF=7.5mA
57 75 ns 3,7
tPHL Propagation Delay Time to Low Output Level 45 75 ns 3,8
tR Output Rise (10-90%) 25
ns 3
tF Output Fall Time (90-10%) 35
ns
CMH Common Mode Transient Immunity at Logic High Output Level VCM=50Vpeak, RL=350ohm, IF=0mA, VO(min)=2V 1000 10000
V/µs 3,9,11
CML Common Mode Transient Immunity at Logic Low Output Level VCM=50Vpeak, RL=350ohm, IF=7.5mA, VO(max)=0.8V -1000 -10000
V/µs 3,10,11

Notes

  1. Bypassing the power supply line is required, with a 0.01µF ceramic disc capacitor adjacent to each isolator. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20mm. The power supply bus for the isolator(s) should be separate from the bus for any active loads otherwise a larger value of bypass capacitor (up to 0.1µF) may be needed to suppress regenerative feedback via the power supply. Failure to provide the bypass may impair the switching properties.
  2. Peaking circuits may produce transient input currents up to 50mA, 50ns maximum pulse width, provided average current does not exceed 15mA.
  3. Each channel.
  4. Measured between pins 1,2,3,4 shorted together and pins 5,6,7,8 shorted together.
  5. This is a proof test.
  6. Measured between pins 1,2 shorted together, and pins 3,4 shorted together.
  7. The tPLH propagation delay is measured from the 3.75mA point on the trailing edge of the input pulse to the 1.5V point on the trailing edge of the output pulse.
  8. The tPHL propagation delay is measured from the 3.75mA point on the leading edge of the input pulse to the 1.5V point on the leading edge of the output pulse.
  9. CMh is the maximum tolerable common mode transient to assure that the output will remain in a high logic state (ie. Vo > 2.0V)
  10. CMl is the maximum tolerable common mode transient to assure that the output will remain in a low logic state (ie. Vo < 0.8V)
  11. For sinusoidal voltages, (I*CML dv/dt)max=pi*fCM*VCMp-p.



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